2019 LLVM Developers’ Meeting: R. Sharma “Lowering tale: Supporting 64 bit pointers in RISCV...”
Why the open web links it
Discusses technical challenges of supporting 64-bit pointers in a 32-bit RISC-V LLVM backend for a GPU ISA.
Linked by 2 independent sites, 2 of them widely read in the 2026-10 crawl of the open web, including washington.edu, llvm.org.